// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
// Date        : Sat Feb 18 00:06:36 2023
// Host        : DESKTOP-E9FP16L running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub
//               d:/study/E203_1/E203_prj/E203_prj/E203_prj.srcs/sources_1/ip/PLL/PLL_stub.v
// Design      : PLL
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7a35tlcsg324-2L
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module PLL(CLK_O_16M, CLK_O_8M388, resetn, locked, 
  CLK_I_100M)
/* synthesis syn_black_box black_box_pad_pin="CLK_O_16M,CLK_O_8M388,resetn,locked,CLK_I_100M" */;
  output CLK_O_16M;
  output CLK_O_8M388;
  input resetn;
  output locked;
  input CLK_I_100M;
endmodule
